The present invention relates to power semiconductor devices, more particularly, to MOSFET devices suitable for high frequency power conversion or RF applications, and to a process for making such devices.
The semiconductor industry is witnessing an increasing demand for DC-DC converters with low output voltage, very fast transient response, and high efficiency that can be advantageously used for high frequency power conversion. When the operating frequency reaches 1 MHz or higher, the power losses of a synchronous buck DC-DC converter will be dominated by the switching losses of output power MOSFETs. It is well known that most switching losses in a power MOSFET occur during charging/discharging the drain-gate capacitance, the so-called xe2x80x9cMiller effect.xe2x80x9d Reducing drain-source feedback capacitance, referred to as xe2x80x9cMiller capacitance,xe2x80x9d is an important approach to improving DC-DC converter efficiency. In addition, decreasing or completely eliminating Miller capacitance would dramatically improve the RF performance of the device. Conceptually, Miller capacitance can be substantially decreased by removing the polysilicon layer overlying the neck region, or by increasing the thickness of the oxide layer underneath the polysilicon layer in the neck region. These concepts are discussed in, for example, the following publications: K. Shenai, xe2x80x9cOptimally scaled low-voltage vertical power MOSFETs for high-frequency power conversionxe2x80x9d in IEEE Trans. Electron Dev., 1990, Vol. 37, No. 4, pp 1141-1153; O. Ishikawa and H. Esaki, xe2x80x9cA high-power high-gain VD-MOSFET operating at 900 MHzxe2x80x9d in IEEE Trans. Electron Dev., 1987, Vol. 34, No. 5, pp 1157-1161; and D. Ueda, H. Takagi, and G. Kano, xe2x80x9cA new vertical double diffused MOSFETxe2x80x94The Self-Aligned Terraced-Gate MOSFETxe2x80x9d in IEEE Trans. Electron Dev., 1984, Vol. 31, No. 4, pp 416-420. The disclosures of these papers are incorporated herein by reference.
Realizing the concepts discussed in the cited papers is a formidable fabrication challenge, requiring a multiplicity of masks, non-self aligned photolithographic steps, and non-standard processing steps. It would be highly desirable to devise a cost-effective, readily manufacturable self-aligned process for the fabrication of power MOSFETs with low Miller capacitance. This goal is met by the process of the present invention.
A process for forming a power semiconductor device with reduced input capacitance and improved switching speed comprises: providing a semiconductor substrate that includes an n-doped layer of epitaxially grown silicon, and forming a thick oxide layer on an upper surface of the epitaxial layer. Prior to formation of the thick oxide layer, a thin pad oxide layer is optionally grown on the epitaxial layer. The thick oxide layer is patterned to form a narrow terraced gate oxide region having a top surface and two side surfaces on the epitaxial layer upper surface. A gate oxide layer is formed on the upper surface of the epitaxial layer, and a layer of polysilicon is deposited on the narrow terraced gate oxide region and the gate oxide layer. The polysilicon layer is anisotropically etched to form tapered polysilicon spacers abutting each of the two side surfaces of the narrow terraced gate region.
A p-type dopant is implanted through the gate oxide layer and a tapered portion of the polysilicon spacers, and the dopant is driven to form P-well regions in the epitaxial layer at its upper surface. A source mask is formed on the epitaxial layer upper surface, and an n-type dopant is implanted through the gate oxide layer and a tapered portion of the polysilicon spacers, then driven to form N+ source regions in the P-well regions.
The process of the present invention further comprises: removing the source mask and forming a passivation layer on the polysilicon spacers, the top surface of the narrow terraced gate region, and the gate oxide layer overlying the epitaxial layer upper surface. Following removal of portions of the passivation layer and the gate oxide layer overlying the P-well and N+ source regions to form P-well and N+ source contact regions, a metal layer is formed that is in contact with the P-well and N+ source contact regions and with a gate contact region.
In another embodiment, the process of the present invention further comprises: removing the source mask and the polysilicon spacers from the epitaxial layer upper surface, and depositing a layer of gate metal on the narrow terraced gate oxide region and the gate oxide layer. The gate metal layer is anisotropically etched to form tapered metal spacers abutting each of the two side surfaces of the narrow terraced gate region, and a passivation layer is formed on the metal spacers, the top surface of the narrow terraced gate region, and the gate oxide layer overlying the epitaxial layer upper surface. Portions of the passivation layer and gate oxide layer overlying the P-well and N+ source regions are removed to form P-well and N+ source contact regions, and a metal layer is formed that is in contact with the P-well and N+ source contact regions and with a gate contact region.